Broken constrain in inline asm. Bytewise access works with a, b, c, d
registers only, thus "r" is wrong, it must be "q". gcc 4.4 tries to
use the si register, which doesn't work and thus fails the build.
From: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
/* prio = ffs(mask ROR vpic->priority_add); */
asm ( "ror %%cl,%b1 ; bsf %1,%0"
- : "=r" (prio) : "r" ((uint32_t)mask), "c" (vpic->priority_add) );
+ : "=r" (prio) : "q" ((uint32_t)mask), "c" (vpic->priority_add) );
return prio;
}